The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for initializing an SRAM device during power-up.
A typical static random access memory (SRAM) device includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value therein, which voltage value represents a logical data bit (e.g., “0” or “1”). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. With CMOS (complementary metal oxide semiconductor) technology, the inverters further include a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as a latch that stores the data bit therein so long as power is supplied to the memory array. In a conventional six-transistor cell, a pair of access transistors or pass gates (when activated by a wordline) selectively couples the inverters to a pair of complementary bitlines.
An SRAM array, being a volatile memory device, does not retain the cell data therein once the array is disconnected from its power supply. Thus, during power-up of the array, the individual cells therein may experience a metastable state in which the two cell nodes initially remain at approximately equal voltages somewhere between the nominal supply voltage value and ground. Under these conditions, the memory cell will experience high current conduction and unwanted power consumption as both the NFET and PFET devices of each inverter simultaneously conduct. In addition to this DC power consumption, a typical SRAM array utilizes a bitline precharging scheme in which the bitlines are precharged to VDD potential during power-up. This provides a further AC current component in addition to the DC current dissipated by the metastable cells.
Excessive power-up currents create power supply problems in both system and test environments. Tester supply ramp rates are carefully adjusted to account for these excessive currents. Furthermore, system power supplies may have to be over-designed to account for the above described initial high-current surge at power-up and prevent power supply stall. Metastability and high currents at power-up can be quite unpredictable and thus cannot be easily managed. Currents in the 10 A range have been observed in an 18 Mb CAM (content addressable memory) array during power-up. As SRAM densities increase with technology scaling, power-up currents resulting from metastable arrays may eventually exceed the capabilities of the tester/system power supplies.
Accordingly, it would be desirable to be able to alleviate the high-current condition created by powering up a metastable memory device such as an SRAM or CAM array.